1. Field of the Invention
The present invention relates to a clock regeneration circuit for regenerating duty ratio of a clock pulse to be used in a logic circuit.
2. Prior Art
A prior art clock regeneration circuit will be described with reference to FIGS. 5 and 6. In FIG. 5, denoted at 1 is an input terminal, 4 is a delay circuit, 5 is an output terminal, and 6 is a D-type flip-flop (hereinafter referred to as D-FF). In FIG. 5, data inputted to a data input terminal (hereinafter referred to as D) of the D-FF 6 is fixed to an H level, and an output of the input terminal 1 is inputted to a clock terminal of the D-FF 6. A Q output (hereinafter referred to as Q) of the D-FF 6 is connected to the output terminal 5, and is also connected to a reset terminal (hereinafter referred to as R) of the D-FF 6 by way of the delay circuit 4.
The operation of the conventional clock regeneration circuit in FIG. 5 will be now described with reference to a timing chart of FIG. 6. FIG. 6 (a) shows a waveform of an inputted clock signal a, FIG. 6 (b) shows a waveform of an output b of the D-FF 6, FIG. 2 (c) shows a waveform of an output c of the delay circuit 4. In FIG. 6 (a), when a clock pulse of the input clock signal a is outputted from the input terminal 1 to the clock terminal of the D-FF 6, the output b of the D-FF 6 in FIG. 6 (b) is changed from an L level to an H level after the lapse of an internal delay time t.sub.1 required from the time when the input clock signal is inputted to the clock terminal of the D-FF 6 until the time when the output b of the D-FF 6 is outputted from the Q of the D-FF 6 (hereinafter referred to as simply as an interval delay time t.sub.1) of the D-FF 6, and is then outputted to the output terminal 5 as an output clock signal b.
At the same time, the output clock signal b is also supplied to the delay circuit 4 wherein the output c of the delay circuit 4 in FIG. 6 (c) is changed from the L level to the H level after the lapse of a delay time t.sub.2 of the delay circuit 4, and is then inputted to the R of the D-FF 6. Accordingly, in FIG. 6 (b), the output b of the D-FF 6 is changed to the L level after the lapse of an internal delay time t.sub.3 required from the time when the output c of the delay circuit 4 is inputted to the R of the D-FF 6 until the time when the output of the D-FF 6 is outputted from the Q of the D-FF 6 (hereinafter referred to as simply as an internal delay time t.sub.3) the and is then outputted to the output terminal 5 as an output clock signal b, and it is simultaneously supplied to the delay circuit 4. The output c of the delay circuit 4 in FIG. 6 (c) is further changed to the L level after the lapse of the delay time t.sub.2, then it is inputted to the R of the D-FF 6.
In the conventional clock regeneration circuit having the arrangement as shown in FIG. 5, the time required from the time when the output of the delay circuit 4 is inputted to the R of the D-FF-6 until the time when a succeeding clock pulse is inputted to the clock terminal of the D-FF 6 needs to satisfy a release time t.sub.rel of the D-FF 6. However, since the pulse width of the output of the delay circuit 4 (which was inputted to the R of the D-FF 6) is equal to that of the output clock signal b, the maximum value of the pulse width allowed by the output clock signal b is expressed by (T+t.sub.3 -t.sub.1 -t.sub.rel)/2 supposing that the cycle is T. Accordingly, in the arrangement as shown in FIG. 5, there is a problem in that the pulse width of the output clock signal is further smaller than the duty ratio of 50%. It is therefore an object of the present invention to provide a clock regeneration circuit capable of obtaining clocks having an arbitrary duty.